System Level Design of Reconfigurable Systems-on-Chip
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By extending Ptolemy II to support HDL co-simulation, the actual cycle-accurate RTL-level implementation of the receiver could be validated together with the same system model and the same kind of analysis could be done [RP]. The second case study concentrated on the usage of commercial tools, aiming to design a reconfigurable noise generator by using Mathworks Simulink and Xilinx System Generator tools [ESJ]. In this case, the facilities for model transformations were already available, so the design flow was much simpler, but on the other hand Simulink provides a single model of time and concurrency, rendering this approach suitable for homogeneous systems only.
As a complement to the first two case studies, another extension to Ptolemy II was added to support the hardware-in-the-loop simulation of subsystems prototyped in FPGA platforms [JO]. The experiences obtained from the reported case studies were then collected and organized as a well defined — though still experimental — design flow [LSI] that allows the successive refinement of an actor-oriented model of the complete system into a final implementation in RTL level HDL, which in turn can be validated together with testbenches also modeled as actors through co-simulation or emulated within FPGA platforms.
Based on the identified design flow, a number of additional experiments and improvements were performed. In [HZ], the flow was used to investigate out-of-order execution in microprocessors containing one or more reconfigurable functional units. To simplify the transition from actor-based models into cycle-accurate HDL models, which had to be done by hand in some of the previous case studies, a first step on implementing code generation techniques was taken on [FM].
Concurrently to the development of the reported actor-based design flow, the MES system-level design group also investigated the possibilities of using UML to support the increase of abstraction on the system. UML was being considered by many industry and academic researchers as a promising SoC specification language, and the group already had previous experience by using UML for internal software development and for SoC design space exploration [IGK].
Your recently viewed items and featured recommendations. Design Patterns for Reconfigurable Computing. The availability of model compilers following this approach is still small, which restricts the adoption of xUML in different domains. Concurrently to the development of the reported actor-based design flow, the MES system-level design group also investigated the possibilities of using UML to support the increase of abstraction on the system. Besides that, constraints such as performance, latency and power must be observed and requirements such as reliability, fault tolerance, correctness data ordering and completion no data loss must be complied. Taming heterogeneity - the Ptolemy approach. Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
The first case studies produced mixed results: Furthermore, the adoption of UML by SoC designers used to validate functionality through simulation is a potential problem that was already hinted by the performed case studies. While UML lacks execution semantics, actor orientation has the coexistence of multiple execution semantics as its major feature. It is then natural to foresee a joint approach of such techniques, so that the shortcomings of one of them are compensated by the strengths of the other.
Furthermore, another reason to combine both approaches is the fact that in many companies there has been the need for integrating different departments in order to cope with the complexity of the design of state-of-the-art systems.
In such cases, as it is nowadays the rule in systems design, the new designs will reuse a large quantity of previously developed solutions, and in such integrated departments a number of solutions may be implemented in UML while others follow the actor oriented paradigm. Keeping that in mind, some initial research was performed on the possibilities of joint usage of UML and actor orientation.
The encapsulation of UML sequence diagrams as actors — which is one of the basic ideas behind the framework to be developed within the proposed project — was explored in [AT]. Early results in a case study with a UML sequence diagram modeling the Chandra-Toueg distributed consensus algorithm [63] within a distributed sensing application modeled as a set of actors were already reported in [ITG]. The design space of MPSoC architectures based on NoCs is very large, allowing designers to customize and optimize a large number of aspects such as buffering schemes, routing, data packet size and format, data coding, transmission modes and QoS strategies.
SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip
Most of the research activities done within the MES Institute address ways to explore such design space and validate possible solutions under different application requirements, as the ones reported in [IGK] for routing and arbitration and in [ZZHG] for buffering. A number of achievements were done in the design and validation of irregular NoC platforms.
Such platforms are needed when the processing cores that are needed by a given application cannot be placed evenly in a mesh-like structure. In [SHZG], novel routing and placement algorithms were explored aiming to support deadlock-free communication among processing cores in such irregular platforms. Besides the inherent design complexity, one of the major factors preventing the wide adoption of NoC-based architectures is the large power consumption overhead they cause.
Relying on previous research that pointed out the correlation between the signal transition activity and the power consumption in interconnects [GO], a number of case studies assessed the potential of reducing the power consumption by coding the data packets sent across the network so that the transition activity on the interconnects is minimized [PIMa]. Promising results were found for very simple coding schemes, because the power consumption increase due to coders and decoders was sufficiently low to be compensated by the savings granted by the reduction of the transition activity [PIMb].
Further activities include the close cooperation with two internationally active groups in this area: The tri-national cooperation addresses regular mesh-like networks and most of the development is done on top of the HERMES platform initially developed by the GAPH group and currently extended by all partners.
For instance, the power reduction approach of [PIMa,b] was already ported to that platform successfully. Current and future work, which are very relevant to this proposal, include the hardware infrastructure to support migration of software and hardware tasks across processing nodes interconnected by a NoC. To do that, a combined solution for an on-chip distributed operating system and for software-controlled node reconfiguration is being pursued.
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System Level Design of Reconfigurable Systems-on-Chip
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